Generally, a Power Management Integrated Circuit (PMIC) includes a High-Side (HS) region and a Low-Side (LS) region in accordance with voltages applied to the regions of the PMIC. The HS region and the LS region are electrically insulated by a device isolation layer. In such a PMIC, a voltage or a current is applied through a metal interconnection crossing over an HS region and an LS region. Also, a predetermined amount of a parasite current and a breakdown voltage between the HS region and the LS region needs to be obtained based on an operating voltage while an arbitrary voltage is applied to a predetermined region of the PMIC or a predetermined region of the PMIC is grounded to allow the PMIC to operate normally. In a state where an arbitrary voltage or a ground voltage is applied to a predetermined region of the PMIC, a breakdown voltage and a parasite current between the HS and LS regions should be higher than predetermined values as compared with an operating voltage so as to ensure stable operations of the PMIC.
When an operating voltage of a related-art PMIC is considerably high, however, an electric field is generated between a metal interconnection and a device isolation layer. Consequently, a sufficient operating voltage is not ensured due to a parasite current and a breakdown voltage.